1. Field of the Invention
The present invention relates to a delay locked loop circuit with a duty cycle correction function.
2. Description of the Prior Art
As generally known in the art, the present invention may particularly be applied to semiconductor memory apparatuses requiring delay locked loop circuits, however, it may also be used for all kinds of semiconductor apparatuses and computer systems requiring delay locked loop circuits.
A delay locked loop (DLL) is a clock generating apparatus for compensating for skew between an external clock and data or an external clock and an internal clock. A conventional DLL with a duty cycle correction (DCC) function is divided into two methods of application. One is a method of realizing negative feedback using a DCC integrator. The other is an open loop method without feedback only in a DCC aspect, in which one more DLL is used.
FIG. 1 is a block diagram of a DLL circuit with a DCC loop realized by the first method. As illustrated in FIG. 1, when an external clock (extclk) is input to a DLL 101, a clock (clkin) whose phase is different from that of the external clock (extclk) by a predetermined amount is generated by the DLL 101 and is provided to a DCC loop 103. In FIG. 1, a loop for feeding back a clock signal (clkout) is a component of the DCC loop 103. However, the loop is illustrated to be separate from the DCC loop 103 in order to clearly represent that a feedback loop exists. The duty cycle of the clock clkin is compensated for by the DCC loop 103. The output clock clkout generated as a result is provided to the outside through an output port of a DLL circuit 100.
FIG. 2 is a block diagram illustrating an example of a differential method of a DLL circuit in FIG. 1. In FIG. 2, CLK and CLKb denote differential signals of an external clock signal. The differential signal CLKb is obtained by inverting the differential signal CLK. IN and Inb denote differential signals of a clock clkin. The differential signal Inb is obtained by inverting the differential signal IN. OUT and OUTb denote differential signals of the output clock clkout. The differential signal OUTb is obtained by inverting the differential signal OUT. As illustrated in FIG. 2, the DLL 101 includes a variable delay line 201 and a phase determiner 209. The DCC loop 103 includes a differential DCC amplifier 203, a level correction amplifier 205, and a DCC integrator 207. An input buffer 211 for converting a clock signal input from the outside into a signal level for an internal circuit can be further included. The phase determiner 209 receives external clocks CLK and CLKb and output clocks OUT and OUTb and determines a phase difference between the external clocks and the output clocks, to thus generate a control signal CTRL for controlling a delay amount in a variable delay line 201. In general, the variable delay line 201 delays the external clocks CLK and CLKb by the delay amount determined by a control signal CTRL so that the external clocks CLK and CLKb have the same phases as those of the output clocks OUT and OUTb. The delayed clocks IN and Inb are provided to a differential DCC amplifier 203 forming the DCC loop 103 in order to compensate for the duty cycle.
The operation of the DCC loop 103 will now be described with reference to FIG. 3. FIG. 3A illustrates the DCC loop in FIG. 2 for the convenience of understanding. FIG. 3B illustrates waveforms of the operations of the DCC loop. When the duty ratios of the clocks IN and Inb are not 50%, a DCC integrator 207 integrates the output clocks OUT and OUTb, to thus generate voltage signals VDCC and VDCCb reflecting the output clocks OUT and OUTb, and provides the voltage signals VDCC and VDCCb to the differential DCC amplifier 203. The differential DCC amplifier 203 controlled by the voltage signals VDCC and VDCCb applies different direct current voltages to high intervals and low intervals of the clocks IN and Inb, to thus generate clocks INDCC and INDCCb. As illustrated in FIG. 3B, in the clocks INDCC and INDCCb, high levels and low levels have different values but the same period. Hereinafter, the clocks INDCC and INDCCb are referred to as “interval correction clock signals”. An output buffer (or a level correction amplifier) 205 receives the clocks INDCC and INDCCb and causes the absolute values of the high level and the low level to be equal, to thus generate the output clocks OUT and OUTb. Hereinafter, the clocks OUT and OUTb are referred to as “level correction clock signals”. The level correction amplifier 205 operates as an output buffer. Accordingly, the duty cycle is compensated for by a DCC loop 300.
FIG. 4A is a circuit diagram of an example of the DCC integrator 207 in FIG. 3. FIG. 4B illustrates a waveform of the operation of the DCC integrator. As illustrated in FIG. 4A, the DCC integrator 207 may include two current sources IDCC, two switches SL and SH, and a capacitor C1 or C2. When the output clock OUT is used for controlling switches, the switch SL is turned on in a low interval of the output clock OUT and the switch SH is turned on in a high interval. It is possible to control switches using the output clock OUTb. When the output clock OUT is used for controlling the switches SL and SH and a low interval is longer than a high interval as illustrated in FIG. 4B in the output clock OUT, the time for which the switch SL is turned on is longer than the time for which the switch SH is turned on. Therefore, charges are accumulated in the capacitor C1. Accordingly, the magnitude of the voltage signal VDCC gradually increases. Meanwhile, because charges are discharged from the capacitor C2, the magnitude of the voltage signal VDCCb gradually decreases. When the duty cycle is not adjusted, the voltage signals VDCC and VDCCb change in proportionate to the duty cycle. When the duty cycle is adjusted, the voltage signals VDCC and VDCCb do not change and maintain a certain value.
FIG. 5 is a circuit diagram of an example of the differential DCC amplifier in FIG. 3. FIG. 6 is a circuit diagram of an example of an output buffer. Such a method has an advantage of obtaining a high level of correctness but has a disadvantage of increasing errors as a frequency becomes lower because locking time is long and an applicable bandwidth is not very wide. This is because toward low frequencies ΔVDCC(b) or ΔVDCCb, corresponding to a duty cycle error, becomes larger beyond an allowable range toward a low frequency.
FIG. 7A is a block diagram of a DCC circuit using two duty locked loops, which is realized by a second method. FIG. 7B illustrates waveforms of the operations of the DCC circuit. The DCC circuit according to the present method includes two DLLs 601 and 603 and an intermediate phase generator 605 as illustrated in FIG. 7A. The DLL 601 outputs a clock (clk1) for the external clock (extclk). The DLL 603 outputs a clock (clk2). The clock (clk1) is obtained by inverting the clock clk2. As illustrated in FIG. 7B, the clock clk1 and the clock clk2 have a relationship in which the high level start edge, the rising edge of a level with a duty of (50−Δ)% in the clock clk1, and the low level start edge, the falling edge of a level with a duty of (50+Δ)% in the clock clk2, occur at the same point of time. The two clocks clk1 and clk2 generated from a DLL block 607 are provided to an intermediate phase generator 605. A clock clkout having an intermediate phase between the two clocks clk1 and clk2 is generated from the intermediate phase generator 605. As illustrated in FIG. 7B, the rising edge of the clock clkout is generated the moment that the rising edge of the clock clk1 and the falling edge of the clock clk2 are generated. The falling edge of the clock clkout has an intermediate phase between the falling edge of the clock clk1 and the rising edge of the clock clk2. What is important is that gate delay in the intermediate phase generator 605 is not considered. In this method, a DCC function is completed through composing of the outputs of the two DLLs 601 and 603. This method is an open loop method only in a DCC aspect. That is, a feedback loop of correcting duty errors little by little, monitoring the duty errors, and making certain that an amount needing correction does not exist.
FIG. 8A is a detailed block diagram of an example of the DCC circuit in FIG. 7. FIG. 8B illustrates waveforms of the operations of the DCC circuit. The first DLL 601 of FIG. 7 includes a first delay line 801 and a first phase determiner 803. The second DLL 603 includes a second delay line 805 and a second phase determiner 807. A buffer 811 of an output port can be omitted if necessary or may have another type. A first dummy delay 813 is inserted into the loop of the second DLL 603 in order to model the time delay of a clock signal in an intermediate phase generator 809. A second dummy delay 815 is inserted into the loop of the second DLL 603 in order to model the time delay of a clock signal in an output buffer 811. When the differential signals CLK and CLKb corresponding to the external clock extclk are provided to an input buffer 817, the input buffer 817 converts the clock signals CLK and CLKb into an internal clock rCLK suitable for an internal circuit and provides the clock signals CLK and CLKb to the first and second delay lines 801 and 805. The internal clock rCLK is delayed by the first and second delay lines 801 and 805 for a predetermined time, becomes the clock clk1 and the clock clk2, and is input to the intermediate phase generator 809. The external clock CLK is provided to the first phase determiner 803 and the second phase determiner 807. The first phase determiner 803 receives the output clock clkout and determines a phase difference between the external clock CLK and the output clock clkout, to thus generate a first control signal CTRL1 for displaying the phase difference, and provides the first control signal CTRL1 to the first delay line 801. A delay amount in the first delay line 801 of the internal clock rCLK is determined by the control signal CTRL1. The second phase determiner 807 receives a feedback clock fbclk2 obtained by the clock clk2 generated by the internal clock rCLK being delayed through the second delay line 805 passing through the first dummy delay 813 and the second dummy delay 815. The first dummy delay 813 does not have a function of generating a signal having an intermediate phase between the received two signals, however, is a circuit for modeling time delay of a clock in the intermediate phase generator 809. The second dummy delay 815 is a circuit for modeling time delay of a clock in an output buffer 811. The second phase determiner 807 detects a phase difference between the external clock CLK and the feedback clock fbclk2, generates a second control signal CTRL2 corresponding to the phase difference, and provides the second control signal to the second delay line 805. The delay amount of an internal clock Rclk2 in the second delay line 805 is determined by the second control signal CTRL2. A small circle toward the output port means inversion of a signal in the second delay line 805. Therefore, the second delay line 805 delays the inverted internal clock rCLK for a predetermined time. As illustrated in FIG. 8B, the circuit of FIG. 8A is formed so that the high level of the start edge, the rising edge of a level with a duty of (50−Δ)% in the clock clk1, and the low level of the start edge, the falling edge of a level with a duty of (50+Δ)% in the clock clk2, occur at the same point of time. The rising edge of the output clock clkout is generated with a time difference corresponding to gate delays at the intermediate phase generator 809 and the output buffer 811 from the rising edges of the clocks clk1 and clk2. The falling edge is also generated with the time difference in an intermediate phase between the falling edge of the clock clk1 and the falling edge of the clock clk2.
The intermediate phase generator 809 is a kind of phase composer. FIG. 9A is a circuit diagram of an example of a non-differential method. FIG. 9B illustrates waveforms of the operations of the intermediate phase generator 809, which are generated at the point of time where the widths of the received two clocks are the same and the rising edge and the falling edge are different from each other. FIG. 9C illustrates waveforms of the operations of the intermediate phase generator 809, which are generated at the point of time where the widths of the received two clocks are different and the rising edge and the falling edge are the same as each other. As illustrated in FIG. 9A, the present circuit is only formed from an inverter. In FIG. 9A, a part 901 marked with a dotted line corresponds to the intermediate phase generator. The remaining parts are for easily understanding the operation of the present circuit. When the phase of an input signal ΦAin leads the phase of another input signal ΦBin, output waveforms are as illustrated in FIG. 9B. The phase of an output signal ΦAB can be adjusted to the middle of the remaining two phases ΦA and ΦB. As illustrated in FIG. 9C, the phases of the rising edges coincide and the phases of the falling edges are different from each other. The result illustrated in FIG. 9C can be obtained. The gate delay was not considered in FIGS. 9B and 9C. FIG. 10 is a circuit diagram illustrating an example of a differential method of an intermediate phase generator. In FIG. 10, k may have a real number value no less than 0 and no more than 1 as a phase composition weight value. When an intermediate phase generator 1000 is an ideal linear circuit, it is possible to obtain a desired intermediate phase when k=0.5.
As noted from the above, according to the second method, an additional time for DCC locking is not necessary because the DCC function is realized by using one more DLL. The second method can be easily realized by a digital or non-differential method. However, the characteristic of the intermediate phase generator is not actually linear. It is not possible to avoid the DCC errors generated by changes in voltage and temperature. Also, such errors increase toward low frequencies.